In testing semiconductor devices by a semiconductor test system (IC tester), the basic procedure of functionally testing of a semiconductor device contains creation of input (drive) stimulus for the device, application of these stimulus and comparison of the output with expected results stored in the test system memory.
For the input application, the test system needs to drive (apply test signals to) inputs of the device under test (DUT) at designated times. Similarly, for measuring the outputs of the device under test, the test system needs to strobe device outputs at a precise time. The timing of input stimulus and strobes is critical in obtaining the correct result and to avoid false pass/fail of the device under test. Hereafter, such input (drive) stimulus or test signals and strobes are also collectively referred to as a test pattern.
Because of the manufacturing process, the actual device outputs are slightly different (even when the device is fault free) from the simulation values or expected results stored in the test system memory. Hence, many times, it is desirable to shift the timing on-the-fly for a portion of the test pattern such as shown in FIGS. 1A-1C. Namely, it is desired that the tester strobes (FIG. 1B) are shifted with respect to the device output (FIG. 1A) only within the time range specified by a shift command signal (FIG. 1C). In other words, it is desirable to dynamically shift a portion of the test pattern to test a specific device output while keeping the normal timing for rest of the test. This feature is desirable for both input stimulus as well as for the strobes at the outputs.
Similarly, for AC parametric test (access time, set-up time, hold time, frequency response, etc. of the device under test), the strobe at device output is continuously shifted until an edge (0-to-1 or 1-to-0 transition) is found. For example, when testing an access time of a certain pin of the device under test, to find out the time length (delay) between a reference point and a rising or falling edge of the pin, the strobe has to be shifted step-by-step to detect the edge.
At the present day semiconductor test system, such timing shift is achieved by running a test pattern multiple times, while each time the strobe timing is modified slightly as illustrated in FIGS. 2A-2E. In this example, the AC test is to measure the response time of the device between the input signal (DUT clock input) shown in FIG. 2A and the edge of the device output shown in FIG. 2B. In the conventional technology, the strobe point of FIG. 2C has to be continuously shifted by producing the test pattern multiple times M1, M2, M3 to measure the delay times t1, t2, t3, respectively. The delay time in FIG. 2D is a time length to detect the rising edge (0 to 1) of the device output and the delay time in FIG. 2E is a time length to detect the falling of the device output.
The foregoing conventional technology is inconvenient and time consuming because the test pattern has to be repeatedly generated while slightly shifting the timing of the particular portion thereof one by one. Further, the conventional method for shifting the timing of the test pattern is costly because it requires a long time to prepare a test program for shifting the time one by one. For improving the test efficiency, there is a need of a new circuit and method for shifting the timing in the test pattern on-the-fly without repeatedly producing the test pattern.